SiN-NP in 50 nm SiN
Using a 6″ wafer, we start with 50 nm of RV SiN, then deposit 40 nm a-Si followed by 20 nm of SiO2. RTP of 1050 C, 100 C/s, 60s. JP patterned the wafer to make standard SEPCON chips. The pores were transferred to the SiN using RIE. The RIE etches faster at the perimeter…