Jamie asked me to post these images of our membranes taken by Dr. Xiao Zhang from Hitachi. They used a 300 kV tool to acquire these micrographs. The spacing between the atoms (striations) tells us the crystallographic orientation; most of the nanocrystals we see are in a (111) orientation. It’s interesting that the perimeter of…
Last week, five wafers were produced – three had a double 3500 A wet oxide growth/strip and two had a single 3500 A wet oxide growth/strip. From Jess’ AFM work, an as-is wafer showed a high density of 5-7 nm particles on the wafer surface. With a double oxide growth/strip, these particles do not show…
Last week I took a series of TEM images from all but one position on wafer 638. Below are the TEMs, histograms, and porosities vs. distance from center plots. “Xpos”, “xneg”, “ypos”, “yneg” indicate which axis the images were taken from. Positive x-axis Negative x-axis Positive y-axis Negative y-axis Wafer 638 porosity vs. position While…
We’ve been assuming that porosity follows a linear relationship with respect to wafer position, but this turns out to be incorrect. I imaged membranes from five points on wafer 620 and found that maximum porosity does not occur at the outer most sample, as previously thought, but instead at r=3. Does this provide a better…
Today I etched wafer 621, which is the pair to 620. While w620 has a relatively low pinhole density, w621 shows a much higher occurence of defects. Since the front-end processing and thermal treatment was identical for these wafers, I believe that the variability lies in the etch process. Looking at the two wafers side-by-side,…
I’ve upgraded the WordPress publisher to version 2.6. The most useful change is the ability to track changes to any post/page, compare revisions, and revert to an older version. Here’s a video showing the changes: https://videopress.com/v/mARhRBcT/fmt_std Additionally, I’ve installed some plug-ins that should make posting and keeping up with new posts easier: There is now…
While Chris and I were in Boston we deposited our membrane stack on a patterned wafer. It was annealed at 1000 C and then etched. Because we didn’t have an accurate deposition rate for Silicon, we overestimated and put down 30 nm (instead of 15 nm). Still, we can see in the TEM that pores…
Wafer 612 was made to mimic wafer 504: 850 C RTP, cool down, 1000 C RTP. Wafer 615 was annealed in two steps: first to 400 C and then to 1000 C (without inbetween cool down). Both wafers showed a lower pinhole density. Wafer 615 had a few “traditional” round pinholes. Wafer 612 had some…
Here is a summary of results for membranes (w510X) that have been annealed without their protective oxide. 800 C RTP @ 10 C/s in susceptor 850 C RTP @ 10 C/s in susceptor 900 C RTP @ 10 C/s in susceptor 950 C RTP @ 10 C/s in susceptor It seems that annealing between 800…
Last week I mentioned that a two step anneal may help with the tears that are forming on the membranes when they are annealed post-etch. The recipe I used was a 10 C/s ramp to 600 C, hold 60 s, 10 C/s ramp to the setpoint, hold 60 s, ramp down. I annealed membranes with…