Stability of 200nm SiO2 + 20nm SiN chips
The plan was to fabricate ~7nm pores on the PDMS-painted 200nm SiO2 + 20nm SiN chips and take IVs overtime, and observe the stability of the nanopore’s size. I fabricated a total of 8 200nm SiO2+20nm SiN chips using the Monolith protocol, to 7 nm. Half of the chips were wetted with the freezer step…