SEM of SiO2 Liftoff samples:
We were targeting a TEOS layer of 300 nm for the SiO2 membrane. The wafers were patterned with ø3 µm pores using S1813 resist (~1.5 µm thick). The target etch time in the Drytek RIE is 4 min 10 s using SF6 and Ar. We will need a thicker resist coating to prevent the RIE etching through it and etching the unpatterned area of the SiO2 membrane. The Drytek was originally designed for etching square ceramic substrates and tends to etch the edge region of wafers compared to the center region. Below are SEM images taken by Josh Winans of the edge and center regions of the wafer.
Figure 1: SEM micrographs of edge of wafer showing thicknesses of different layers. Note that the etch depth into the poly-Si is much greater for the sample taken near the edge of the wafer.
First, it is apparent that the TEOS layer was actually more like 130 nm, not 300 nm as targeted. Unfortunately, we did not verify this thickness at the time of deposition. Clearly, we need to calibrate this deposition. Next, it is clear that the S1813 resist is getting etched away prior to the end of the RIE etch, because the pores are more like 3.5 µm in diameter. The RIE step was set for etching through a 300 nm SiO2 layer, so the underlying poly-Si also got etched. Because of the higher etch rate near the outer edge of the wafer, the etch depth into the poly-Si is much greater in that region compared with the center of the wafer.
Figure 2: Top-down SEM micrographs of SiO2 membrane taken from near wafer edge of sample. Note this sample had been exposed to 10 s 10:1 BOE dip followed by XeF2 etching to achieve membrane liftoff from the substrate wafer.
UPDATE 5/5/14: Kelly & I did a test on one of our unpatterned wafers to double check the TEOS layer thickness, and found that it is 310 nm. The reason it is ~130 nm in the lifted off membranes is because the micropore patterning was done in the Drytek Quad for 490 s using S1813 resist. Apparently, the resist was etched away less than half way into the etch.