TEER and Pinholes

One of Christine’s projects was to determine if pinholes affected electrical resistance (TEER) measurements.  She summarized her work here.  I collected her data and did some negative controls to finish this work up.  Here’s the graph:

The “no membranes” data is from Sepcon transwells with pnc-Si chips but without membranes (I broke them before assembling the Sepcon).  As you can see, this is ~100% of the resistance of chips with membranes.  This means that the pnc-Si membranes do not act as a significant resistance to ion flux in the Endohm and the resistance of the active membrane area is essentially zero.  Since pnc-Si with and without membrane is about the same, there is no way to detect a pinhole number-TEER trend.  Also notice that the data is pretty noisy (n=3,3,2,2).  This is due to the geometry of the Sepcon transwell – it doesn’t fit well in the Endohm.  The Endohm electrode separation depends on how “tall” the Sepcon is (i.e., how I cut it with the Dremel).  Based on my experience, the differences in Sepcon transwell geometry can change TEER measurements by ~20 ohms.  To get solid TEER data with our devices, I think the housings need to be designed to fit in the Endohm.  That said, cells cause the TEER of pnc-Si devices to go up by a few hundred ohms, so geometry variability shouldn’t be too much of an issue for monolayer characterization.