Production updates

There’s been a lot of production in the last month and we’re still sorting through the data, but here is a synopsis of some key findings.  All films were deposited with the AJA tool.

Film reproducibility

Week-to-week variation in pore morphology has never been noted explicitly due to the rapidly changing conditions we place on production.  Below, I show two wafers that were created a week apart under identical deposition and anneal conditions.  Although the distribution is slightly different, the cutoff and porosity are very similar.

Center-to-outside uniformity

We no longer have non-uniformity with respect to position on the wafer.  I attribute this to the increase in film thickness uniformity we are able to achieve with the AJA tool.

Deposition temperature

There does not seem to be a drastic change in morphology between films deposited at room temperature and elevated temperature.  There is a slightly higher density of pores with the RT film.

Bias

Increasing substrate bias during deposition increases both porosity and cutoff.

Ramp rate

We have recently started to experiment with the RTP ramp rate (w/o susceptor).  The two membranes below were annealed at 1000 C with a ramp rate of 10 C/s (left) and 100 C/s (right).  It seems that increasing the ramp rate tightens the distribution and lowers the cutoff.  By ramping faster, we’re reaching the nanocrystalline state sooner and lock into a smaller pore distribution.  With a slower ramp rate, we “ease” into crystallization and form larger pores.

Susceptor

Annealing inside the susceptor seems to form larger pores when compared with RTP w/o susceptor.  This is an effect similar to slower vs. faster RTP ramp rates.

Clues on pore formation

Chris:

I’m not sure if you noticed this image in the wafer summaries, but I thought you may be interested.  It is a 5 nm thick “a-Si” film that was deposited at 450C with no further annealing.  After forming the membrane and imaging, Dave and I found a fairly distinct ~5nm nanocrystal in the lower left corner.  This is a fairly rare feature, but strikes me as quite surprising in a sputtered film at this low of a temperature.  If our films are actually pre-seeded with a low density of these rogue nanocrystals, the zone crystallization that we discussed in the last NRG meeting would not be surprising.  Obviously, crystallization would start at a considerably lower temperature at these features, and depending on the thermal ramp and growth rate, the film could be mostly crystallized before the normal nucleation/growth process gets a chance to start.  We have been planning to explore the effects of deposition temperature at some point, and perhaps we should take a closer look at the “amorphous” films.

Philippe:

is this film a free standing film? If the answer is yes, then could it be electron-beam induced crystallization? I am thinking of this because 450C is definitely well below the accepted crystallization of a-Si (around 580C or so). Do I also see pores or pore precursors in that picture?

Chris:

This is a free-standing film.  At 5nm thick we are seeing the voids that you mention – they appear to be at grain boundaries in the film (not-crystalline grain boundaries, but the grains that develop when any film starts to grow on a non-matching surface – there’s always some nano-clumping).  While imaging, I went to other areas where no crystallinity was observed and dwelled for 10X the time at a comparable beam size, and saw no changes in the film, so none of us thought the beam could have induced this feature.   We did not have time to search around much, but this was the only clearly crystalline feature that we found.

I suppose that we really don’t know when this feature formed.  It could have formed during deposition.  It could have formed when the etch penetrated the wafer and the strain in the a-Si changed rapidly (@~100C).  Or it could have somehow been induced by the electron beam, although it seems unlikely.  We’ll keep this in mind as we image other films.

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3 Comments

  1. Just a couple of questions/comments I had regarding production:

    Have we intentionally tried underetching any wafers yet to see if that reduced pinholes?

    I mentioned a while back that I though wafers 686/687 might be useful to look at, but as far as I know they haven’t been etched yet.  Could we try etching (or underetching) these?

    Also, in order to keep track of wafer location, could we write whether they’re in Hopeman or Goergen in the summaries?  I think when they make it over to Goergen, the person receiving them could edit the summary.

  2. Jess –

    No plans have been set to under-etch.  To me this seems like a temporary solution that is hard to control.  I would like to run an experiment with the Megasonics cleaner before we try anything too drastic.

    Sorry about 686/687, we’ve been swamped with etching current production.  Are you looking for smaller cutoff SepCon samples?  Check for SC 062-067 soon.  These were annealed at various temperatures and might hit the range you’re looking for.

    As for keeping track of wafer location, if nothing is written you can assume that it is still in Hopeman.  I guess Nakul is the one who is the first to touch the wafers in Goergen so maybe he could just add a note to the wafer summaries?

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