Wafer 404
Last week I reported wafer 403 showed uniformity across all positions but had a huge amount of pinholes. Wafer 404 (TEOS process & thermal oxide base) was initially annealed at 1000 C and then annealed again at 1000 C for 5 minutes in the RTP. The second anneal helped with the sputtered oxide film quality and reduced the number of pinholes (though it did not completely eliminate them, and most membranes still have 1-2 defects). I think that depositing again at a higher temperature should reduce the pinholes further.
(0,-2) – 50kx
(3,0) – 50kx
(0,4) – 50kx
The three samples had similar average pore sizes and cutoffs, but (0,4) showed slightly higher porosity. The slight variation is something to keep an eye on. These were annealed initially without the susceptor, so a slight variation in thickness may have affected optical absorption in the RTP and thus caused a difference in porosity.
Notes:
- These images were taken with URMC’s newest TEM. It’s pretty slick. I’ll be forwarding the TEM pixel:nm conversions to Jim so he can post them under resources. You can tell which images came from which tool by the size bar style. Big white font = new Hitachi (URMC), big black font = old Hitachi (URMC), small black font = old JEOL (R/C)
- It seems that exposure under the EM beam causes pores to “shrink”. This is a first time occurrence and we have only noticed this under the new Hitachi TEM. There may be something different about the beam intensity in this system (i.e. so intense that it is “melting” the crystalline material into amorphous matter).
- The sputter heater is now installed so we can deposit at elevated temperatures again. This should help with film density and reduce pinholes.
- A high purity oxygen feed has been added to the RTP. This means we have the ability to grow oxide and oxidize samples in Goergen now.
- The HF etch resistance of our pnc-Si material seems to be back. For a long period of time, the membranes were “dissolving” in HF after a moderate treatment indicating partial oxidation of the silicon film during processing (most likely deposition). This should open the door for “float-off” applications. One idea is to lift the silicon membrane material off the silicon substrate and place it on a thin TEM grid for microscopy applications. More on this soon…
- No signs of cigarette burns, comets or other membrane eating beasts in this last set of wafers. We’ve changed several things in the production process, so it’s hard to say what has made the contamination go away. Let’s hope it’s gone for good…
