AJA RTP temperature series
In the last few weeks, the production team has focused on making strong, stable, porous material with the AJA sputter system. In the process, we’ve RTPed a wafers over a wide range of temperatures under different deposition conditions. We found that it’s possible to make membranes that range from non-porous to highly porous along with several intermediate morphologies. Below is a panel of three membranes that were deposited under identical conditions and RTPed at 700 C, 775 C and 1000 C.
Between SC 021 and SC 023 we demonstrate size tunability. There are several interesting things to note about SC 020. This is the first time we’ve seen such a distinct amorphous/crystalline segregation. Pores appear to form around the crystalline clusters, which explains the “pearl necklace” arrangement we’ve seen. This is a major clue to the pore formation process. We’ve always speculated that crystallization is necessary for pore formation and this image furthers that argument.
I think SC020 is very exciting because this is the first time we’ve been able to see the crystallization process in action. There are a number of features that I find interesting, but I would like to take a closer look using the URinc scope before speculating. However, I think it’s clear that this zone pattern of crystallization is causing or is indicative of the pearl necklace effect and elongated pore morphologies that have become more common. In general, I would like to suppress both effects.
These effects seem to be most pronounced in the AJA material. However, I’m curious about whether it’s the deposited material or the anneal that is the root cause. Back when the CVC tool was depositing material like this, we did not have a susceptor and were annealing using the RIT RTP. At that time, ramp rates were in the 100-200 C/s range and overshoot spikes to slightly higher temperature were unavoidable. With the susceptor, Dave has made beautiful textbook thermal profiles with smooth 10C/s ramp rates and little or no overshoot. It is recommended that susceptor ramp rates be limited to ~50C/s, so we have been working safely below that limit. Also keep in mind that the wafer sees no optical radiation inside the susceptor which likely affects the local temperature of the silicon layer during the anneal. Also keep in mind that the absorption of a-Si and nc-Si are very different (after crystallization our Si film becomes much more “clear” in the red-IR, but more opaque in the UV), which may be important when using optical energy to drive the process. If this were an important effect, it could make the phase change extremely rapid outside the susceptor. It will be interesting to see images of TEM041 and TEM042, where we annealed w/o the suceptor.
Do I see ‘background’ pores in SC20?
Jim, are you referring to the lighter spots in the amorphous region? I believe those are just areas of thinner material, not through-holes.
Yes. I didn’t think they were actual pores. I’m trying to point out that background in this sample resembles the background that we saw with the CVC membranes.
Yes, it’s unclear what that background pattern is and why it goes away in the crystallized material. I think it is a bit different from the pattern in the CVC material, but the origin may be similar.