Electrical Characterization of AJA Sputtered Oxide (Initial Experiment)
The electrical properties of 20nm and 50nm thick sputtered oxide is currently being investigated. Capacitance-Voltage (C-V) and Current-Voltage (I-V) tests are achieved by fabricating 200um-4kum diameter capacitor “dots” using Lesker SiO2 targets and flash-evaporated aluminum (CVC). A GCA stepper is also used during photolithography for 5X image reduction.
The purpose of the experiment is two-fold:
-To provide accurate oxide charge data to Jim West of John Hopkins. (C-V test)
-To determine the leakage current and breakdown voltage of our oxide for future van der pauw resistivity measurements of doped pnc-Si (I-V test).
Initial tests were conducted with three samples having the following conditions:
–20nm SiO2/25W bias
–50nm SiO2/25W bias
–50nm SiO2/0W bias
Some results for the 20nm SiO2 sample are shown below:
Some results for the 50nm oxide with no applied bias are shown below:
It is important to note that some of the data calculated by the software (left of the plot) may be inaccurate. This is because the software attempts a best-fit by interpolation:
To correct this, Rob Manley (RIT Microelectronic Engineering) was kind enough to give me the macro he authored that performs a more accurate best fit:
Using this simulator, highly accurate oxide charge and breakdown voltage values can be obtained.
Several samples were tested thus far, so this post only scratches the surface. Future experiments will investigate the effect oxide annealing (using standard conditions) and testing the oxide quality from different target vendors.