Stability of 200nm SiO2 + 20nm SiN chips
The plan was to fabricate ~7nm pores on the PDMS-painted 200nm SiO2 + 20nm SiN chips and take IVs overtime, and observe the stability of the nanopore’s size.
I fabricated a total of 8 200nm SiO2+20nm SiN chips using the Monolith protocol, to 7 nm. Half of the chips were wetted with the freezer step (place gasket/chip/cell complex in freezer for a few min), and the other half were wetted without the freezer step. I don’t have any before and after images of the chip, but looked at the chips under a microscope, prior to fabrication, to ensure the holes weren’t covered with PDMS.
These chips fabricate fairly quickly (especially compared to the Monolith chips) and consistently took ~6min to fabricate. A typical fabrication curve is shown below (identical for with and without freezer step).
On almost all chips, both with and without freezer step, there would be lots of back and forth between conditioning and IV measurements. ie. The pore would condition, hit desired pore size, after one IV or multiple IVs, the size measurement indicates a pore size smaller than desired size and return to conditioning.
This made the conditioning of these chips fairly long, because they would need to condition multiple times. But once they were fully conditioned, the pore remained fairly stable.
Below is an example of a pore (with freezer step).
Left overnight on my desk in petri dish sealed with parafilm. The first measurement that yielded a pore size of ~7nm was taken before reflushing and the rest were taken after reflushing in LiCl. Thus, the slight growth in pore size to ~8.5nm was most likely due to the reflushing.
I made one pore (with freezer step), but changed increased conditioning voltage. This seemed to quicken the conditioning process because the pore didn’t have to re-condition at all this time. (or might have just been luck)
This pore can be seen below. It is also very stable.
Overall, these chips seem fairly stable and are quick to fabricate!
Conclusion:
- The stability of the chips shows that the nitride batch isn’t the problem
- These chips are quick to fabricate, thus wetting is problem for the Monolith chips — there will be a forthcoming post about this
These tests included NPN too, right?
Yes, these stability tests included NPN!
Great. And thanks for this post Michelle.
Can you explain the freezer step a bit more carefully? Do you start in a humid container and transfer to the freezer? Are you concluding that this step provides no benefit for the transfer process? If so, it may help with the monolith?
For the freezer step, I just assembled the half cell (ie. put the plasma-cleaned gaskets and chip together on a half cell), done at room temperature/humidity. Then, I put the assembled half-cell into a tupperware container and transfer it to the freezer, leaving it in there for a few min (~5min).
Based on the results, there doesn’t seem like there’s much of a difference between using the freezer step and not using it.
As for the monolith, most of the experiments I’ve done involved using the freezer step. Currently, we’re using a new protocol, which involves a vapourizing step using a vacuum instead.
Sorry I made a mistake, the stability of the chips in this post didn’t have NPN on them, but they were from the same monolith batch which did have NPN on them!