Temperature series w/ 20 nm & 40 nm oxide

Last week, a RTP temperature series was performed on 15 nm Si membranes with 20 nm and 40 nm oxide layers.  The purpose of this study was to 1. evaluate the effect of a thicker oxide on pinhole density and 2. identify a dependence of morphology on oxide thickness.  Below are two graphs summarizing the average pore diameter and porosity of the membranes in this study.  All anneals were performed inside the susceptor with a ramp rate of 50 C/s.

Unfortunately, there was a mix-up and we missed the 20 nm oxide 950 RTP condition.  There are a few things to note from this data:

• The porosity changes from < 1 % to > 3 % in the RTP temperature range 900 C – 1000 C.
• The porosity in the 20 nm oxide samples was consistently higher than the 40 nm oxide (@ 900 C and 1000 C RTP), while the average diameters were very similar in both oxide thicknesses.  The trend in porosity may be artificial due to the small sample size.

Here are representative TEM images of wafers at the three temperatures.

The yield data is plotted in units of “samples loss to pinholes” i.e. how many samples on the wafer had at least one pinhole over the active area.

There is a clear trend of increasing pinholes with annealing temperature.  In fact, if you omit the 20 nm 900 C wafer that is an outlier, the trend becomes much more clear.  From this data set, it seems the 20 nm oxide outperforms the 40 nm oxide – somewhat counter-intuitive.