Porous TEM windows fabrication using CsCl self-assembly

We’ve been wondering about the effects of membrane stresses on discoloration rates.  This was spurred by Vlassak’s visit and his ideas about stress and membrane stability. In this experiment, I used w501, no RTP, in the oven in RPMI+10%FBS.  All of these samples were in the Sepcon format: chip sealed with a fat O-ring, chip…

This post is meant to conclude the work that I have completed this summer with the double slot single pass devices; recently I have conducted additional experiments and collected ultrafiltration data. In my previous post, “Single Slot Inverted-Chip and Double Slot: Single-Pass Dialysis Devices” https://trace-bmps.org/single-slot-inverted-chip-and-double-slot-single-pass-dialysis-devices/ I was exploring how various analyte / dialysate flow rate…

Glavan et al 2013 Lab on a Chip This paper from the Whitesides group details an interesting way to fabricate paper-based microfluidics. They treat ordinary paper with a fluorinated silanization process to render it hydrophobic, and  use a Silhouette cutter to scratch a channel into the paper. When covered with double-sided scotch tape, conduits are…

Nanobattery Paper Nanobattery Supplement   I have long desired to make energy storage devices with our nanomembranes (supercapacitor post), mainly because they would be really great separators, having both excellent charge conduction and physical barrier resistance due to the porosity and material properties of silicon. Other groups have begun to take advantage of the increased…

We used 4″ wafers with 40 nm pnc-Si on 50 nm RV SiN (RTP 1050 C, 100 C/s, 60 s). JP ran a series of RIE times from 10 to 50 s with 10 s intervals.  (We had initially planned on starting at 70 s based on experiments with 6 ” wafers, but fortunately JP chose…