Burst Pressure Probability II
This is a follow up to Mohammad’s previous posts: “Burst Pressure”, and “Burst Pressure Probability”. Josh and I had Mohammad’s wafer remade, and burst several 30nm thick pnc-Si TEM chips to add to Mohammad’s earlier data. Pore size still needs to be verified using the TEM. Burst pressure data was gathered for chips with constant perimeter, minimum dimension, and area. The burst pressure assembly was used to break the chips, as shown below:
Pressure was steadily increased using the pressure gauge until the chip broke, and the burst pressure was recorded using the manometer. There were several instances where multiple windows quickly burst, and the first window to break could not be identified. The data below only represents the chips where a single window broke, decreasing the sample size. Also, there are three bars below without error bars, as these represent only one case of one window breaking for a particular window type.
For the chips where perimeter was held constant, the windows with the largest areas broke most often. When the minimum dimension was held constant, the window with the largest area was also most likely to break. For constant area, the window with the more square shape broke most frequently.
We still have single window 30nm thick pnc-Si TEM chips for ten different window sizes remaining, with the expectation that we will have more concrete burst pressure data for a given window size.
Excellent data and beautiful presentation. The data seem to make the case that the formats that experience maximum deflection will burst first. Time to put this on solid theoretical ground with a little modeling.