Last week I reported wafer 403 showed uniformity across all positions but had a huge amount of pinholes. Wafer 404 (TEOS process & thermal oxide base) was initially annealed at 1000 C and then annealed again at 1000 C for 5 minutes in the RTP. The second anneal helped with the sputtered oxide film quality…
Wafer 403 was processed last week using the new thermal oxide/TEOS steps outlined in the previous posts. I took images from six positions at different radial positions on different axis. All six samples looked relatively uniform! (1,0) – 35kx (0,-2) – 35kx (3,0) – 35kx (4,0) – 35kx (0,5) – 35kx We know that the…
Production was scarce last week because we ran into some problems with our patterning/etch process. The first two wafers I attempted to etch did not react with the EDP because there was a thicker than normal layer of oxide remaining after our lithography step which prevented the EDP from attacking the underlying bulk silicon. We’ve…
Today I looked at a wafer (391) that had been annealed in the RTP on top of a 6″ wafer substrate. The idea is that the six inch substrate would create a “shadow” around the 4″ wafer which would improve thermal uniformity by blocking the multiple reflections from the lamps inside the chamber. Here is…
We’ve got pores! Unfortunately, we are still being plagued by an unknown contamination that seems to be “eating” away at our membranes. This would explain why we’ve been having a hard time separating. We also observe a strong radial dependence in porosity AND size with these RT deposited films. In the past it was limited…
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Six wafers (385-390) were produced last week with the new Solaris 150 RTP system. Good news: We now have much better control/feedback compared to the RIT setup. There are two thermlecouples on the wafer tray that monitors the front and back portion of the wafer. The new unit allows us to independently modify the front/back/bottom…
Last week’s production yielded six wafers, all deposited at room temperature. Here were the annealing conditions: Wafer 334, 343 – RTP @ 975CWafer 341, 344 – RTP @ 975C + FA @ 1000CWafer 342, 345 – FA @ 1000 C Pinhole density was moderate along the edges of the wafer, with one or two pinholes…
Last week we processed wafers 335 – 340. Our goal was to track down the source of Cu contamination. We sputtered membrane films both at room temperature and at 400 C. Our thought was that the RT dep. would not show contamination if the sputter heater was indeed the source of our Cu. It turns…
Last week, I took some of Jess’ 20 nm Au colloids and placed them on a membrane for imaging under TEM. I took images at each of our standard magnifications. Using Mike B.’s pore counting program, I generated statistics and calculated the pixel-to-nm conversion ratio assuming the gold colloids were 20 nm (< 10% variation)....