Shadow-Masking Microporous and Nanoporous Materials with Silicon Nanomembranes

ByGreg Madejski

Summary:

The fabrication of NPN relies on the formation of pnc-Si over a non-porous SiN film, then etching the pattern of the pnc-Si into the SiN. I used the same concept to replicate the dual-scale nanomembrane style (microporous+nanoporous) featured in Alec’s work, as well as create a porous/nonporous nanomembrane substrate, by using existing SiN or NPN chips as shadow masks. Basically, flip a silicon nanomembrane on top of a target substrate, and etch the pattern of the pores into the substrate, using our standard etch process at URnano. Surprisingly, the masking behavior is good to a few microns over the course of etching ~100 nm silicon nanomembranes. Some optimization needs to occur, but this should work well for copying pore patterns in a variety of settings without having to do a lithography process.

Shadow Mask Concept

Dual-Scale Nanomembrane Procedure

  • Clean Etch chamber by using a 100 W Argon Plasma (50 SCCM Ar) for 2 min, then season the etching chamber with standard SF6 recipe (120 sec).
  • Take a substrate chip (100 nm NPN) and a microporous masking chip (400 nm thick) and lay the masking chip over the substrate chip
    • Alignment done by hand with tweezers. Larger chunks of chips for batch processing should be easier to align.
  • Use the standard SF6 recipe to etch into the NPN
    • 15 SCCM O2
    • 30 SCCM SF6
    • 10 SCCM CHF3
    • 100 W FWD PWR (0-2 W REF)
    • Base Pressure 5e-5 torr (tolerate up to 1e-4 torr)
    • 30-50 mTorr Etch Pressure
    • Timed etch of 120 sec (this is probably overkill for this process)
  • Remove chip stack and gently slide mask off of the substrate chip.

Microporous Transfer into NPN

Example of transfer process. Etched regions are clearly visible. I have found that it is more likely to produce completely intact chips with fewer windows.

 

Microporous Pattern Transfer Bright Field Image. Non porous region (royal blue, top left), nanoporous region (tan, top right), micropatterned non-porous (orange, bottom left), dual-scale nanomembrane (gray, bottom right)

 

Example shadow masked pore etched into substrate. The pore is dilated to about 3800 nm, compared to a nominal 3000 nm mask.

 

Interstitial space between masked pores. Membrane appears thinned.

 

20 deg tilt. 35000x. Measured in the masked region, the pores seem to be unaffected by the etching process (35-40 nm sidewalls, nominally 100 nm thick)

 

20 deg tilt. 35000x. Measured in the interstitial etched region, the pores are beginning to merge and enlarge. (25-30 nm sidewalls, suggests 60-70 nm thick)

 

NPN-Pattern Transfer Procedure

  • Clean Etch chamber by using a 100 W Argon Plasma (50 SCCM Ar) for 2 min, then season the etching chamber with standard SF6 recipe (120 sec).
  • Take a substrate chip (~50 nm non-porous SiN) and a nanoporous masking chip (100 nm thick) and lay the masking chip over the substrate chip
    • Alignment done by hand with tweezers. Larger chunks of chips for batch processing should be easier to align.
  • Use the standard SF6 recipe to etch into the NPN
    • 15 SCCM O2
    • 30 SCCM SF6
    • 10 SCCM CHF3
    • 100 W FWD PWR (0-2 W REF)
    • Base Pressure 5e-5 torr (tolerate up to 1e-4 torr)
    • 30-50 mTorr Etch Pressure
    • Timed etch of 60-70 sec (this is a very unforgiving process)
  • Remove chip stack and gently slide mask off of the substrate chip.
    • Some remnants of the masking membrane remain

 

60s Etch transfer with NPN shadow mask into 50 nm thick non-porous SiN. The pore pattern is completely blown out, but there are no-through pores present. Free-standing membrane survived etching process.
70s Etch transfer with NPN shadow mask into 50 nm thick non-porous SiN. The pore pattern is completely blown out, and individual pores have now merged due to the lack of pattern fidelity. Membrane did not survive etching process.
70s Etch aligned anaglyph. I estimate the thinning of the membrane from the etching process could be down to 20-30 nm.

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