Even though we don’t have defect free membranes, I wanted to tweak the gold setup using membranes with pinholes. Previously I was using the small scale diffusion chamber that I use for protein separations. This setup has a retentate of 2-3 uL and a filtrate of 60 uL. To do particle sizing using the Malvern…

We’ve been wondering about the effects of membrane stresses on discoloration rates.  This was spurred by Vlassak’s visit and his ideas about stress and membrane stability. In this experiment, I used w501, no RTP, in the oven in RPMI+10%FBS.  All of these samples were in the Sepcon format: chip sealed with a fat O-ring, chip…

Last week, I repeated Anant’s experiment which aimed to eliminate edge effects by painting over chips with nailpolish. I painted the entire well side of the chip but tried to keep the wells clear of polish (“painted back”) and I covered just the edge of a chip but tried to keep polish off the well…

I got a couple of wafers from Chris last week – 50nm oxide deposited at room temperature or 450 degrees.  For each wafer, I saved the zsensor (top), phase (middle) and zsensor (bottom) scans.  I also calculated the roughness (the table looking thing on the bottom of each image.  I had some problems with imaging…

First off – OK now on to the science. Wafer 747 has a huge amount of pinholes, and in this study I wanted to see how these pinholes would effect electroosmosis.  I will show results here from two experiments with these holey membranes.  These membranes have a lower rate of electroosmosis than previous tested membranes. …

I wanted to do some more fluroescent imaging in transwells to look into background fluroescence.  This was mainly motivated by my inital study.  These are HUVECs stained with 5uM CMFDA and 10uM Hoechst 33342, fixed in formaldehyde and imaged on the Zeiss at 10X.  This was 6 hours after seeding.  Before acquiring the images, I…

I did an experiment earlier this week in the Sepcon and flat format. I intentionally broke membrane windows so that I could compare chips with no intact membranes vs. chips with 1 intact membrane (and also the effect of autoclaving). Unfortunately, all of the flat chips discolored overnight, so I couldn’t see any differences between…

Last week we attempted to mimic our standard CVC recipe in the AJA system (15 nm Si, 450 C deposition temp, 1000 C RTP).  I should note that the protective oxide thickness in the AJA membrane was 20 nm (not 40 nm as it was in the CVC).  Below are two images comparing the AJA…